1. Technical Field
The present invention relates to a thin film transistor used for an active-matrix-type liquid-crystal display and a method for fabricating the thin film transistor, and a liquid-crystal display panel using the thin film transistor.
2. Prior Art
An active-matrix-type liquid-crystal display unit using a thin film transistor realizes displaying by arranging gate electrodes (Y-electrodes) and data electrodes (X-electrodes) like a matrix, injecting liquid crystal between a TFT array substrate configured by arranging thin film transistors (TFTS) at intersections of the matrix and a substrate facing and superimposed above the TFT array substrate, controlling a voltage to be applied to the liquid crystal by the thin film transistors, and using the electro-optical effect of the liquid crystal.
In this case, a normal-stagger-type (top-gate-type) structure and a reverse-stagger-type (bottom-gate-type) structure are known as structures of a thin film transistor. FIG. 7 shows a typical structure of a normal-stagger-type (top-gate-type) thin film transistor. As shown in FIG. 7, the top-gate-type thin film transistor is configured by forming an opaque film 102 on an insulating substrate 101 such as a glass substrate and providing an insulating film 103 made of silicon oxide SiOx, silicon nitride SiNx or the like on the opaque film 102. Moreover, a drain electrode 104 and a source electrode 105 which are respectively configured of an ITO (indium-tin oxide) film are provided on the insulting film 103 by keeping a channel interval, an amorphous-silicon film (a-Si-film) 106 for covering the electrodes 104 and 105 is provided, a gate insulating film 107 made of SiOx, SiNx or the like is provided on the film 106, and a gate electrode 108 is provided on the film 107, and thereby an island-shaped region referred to as a-Si island is formed.
As a process for fabricating the thin film transistor, there is the so-called 7PEP (PEP: Photo Engraving Process) structure. In case of the 7PEP structure, the drain electrode 104 and source electrode 105 respectively made of an ITO film are patterned and then, the a-Si film 106 is formed through the CVD (Chemical Vapor Deposition) art and patterned like an island. Thereafter, the gate insulating film 107 is formed through the CVD art and patterned into a predetermined shape. Thereafter, a TFT is completed by forming, for example, an aluminum (Al) film as the gate electrode 108 through sputtering and by patterning the film.
However, because the number of steps increases in case of the 7PEP structure, a next-generation 4PEP structure requiring a less number of steps is proposed. The 4PEP structure is configured by etching the gate insulating film 107 and a-Si film 106 below the gate electrode 108 at the same time. That is, the gate electrode 108, gate insulating film 107, and a-Si film 106 are continuously etched through one-time patterning process by using a gate-electrode plating pattern as a mask. Therefore, the 4PEP structure is very superior in reduction of the number of manufacturing steps.
Though not concerned with reduction of the number of manufacturing steps, there is the official gazette of Japanesse Published Unexamined Patent Application No. 1-68968 as a background art relating to an electrode structure of the present invention. This official gazette discloses a thin film transistor art of arranging a source electrode and a drain electrode in parallel with each other and moreover making these electrodes orthogonal to a gate electrode.
Moreover, a display data signal and a scanning signal are supplied to a drain line and a gate line connected with a thin film transistor from an external unit. In general, a gate line is connected to a gate electrode on an insulating film made of SiOx or SiNx provided on an insulating substrate. Therefore, portions corresponding to the gate insulating film 107 and a-Si film 106 below the gate electrode 108 in a thin film transistor structure are generally removed in case of a gate-line structure excluding an a-Si island.
However, when using the above 4PEP structure in order to reduce the number of steps, a structure similar to an a-Si island is also formed on a gate line because etching and forming a three-layer film through a patterning process once. That is, the a-Si film 106, and gate insulating film 107 unnecessary for the structure cannot be removed from a gate line exceeding an a-Si island and thereby, the films 106 and 107 are directly formed.
FIG. 8 is a top view of a thin film transistor under the above state. A TFT necessary as a liquid-crystal display panel is an a-Si island 111 formed on a gate electrode 108 serving as a protruded portion of a gate line 109. However, another TFT is present on the gate line 109 other than the a-Si island 111 due to the above 4PEP structure. Therefore, a leak current shown by arrows in FIG. 8 are generated from adjacent other data lines 110, adjacent other drain electrodes 104 or the like, and flows into a source electrode 105 and thereby, an extra current flows through a display electrode 112. As a result, no sufficient potential is written in a pixel due to an extra current (crosstalk) and this insufficient write causes extreme deterioration of a display image.
The present invention is made to solve the above technical problems and its object is to reduce the number of necessary steps in a thin-film-transistor manufacturing process and prevent an abnormal potential from occurring due to a leak current from other data lines.
It is another object of the present invention to provide a thin film transistor capable of preventing flickering or sticking due to the change of capacities Cgs between a gate and a source even if a pattern is shifted between a gate line and a signal line.
To solve the above problems, a thin film transistor of the present invention is mounted on a predetermined substrate and provided with a gate electrode formed into a predetermined pattern, a semiconductor layer formed correspondingly to the patterning of the gate electrode, a pixel electrode interposed by the semiconductor layer, and a signal electrode interposed by the semiconductor layer by keeping a predetermined interval from the pixel electrode. The signal electrode is formed at a position for preventing crosstalk running from an adjacent signal electrode to the pixel electrode through the semiconductor layer.
In this case, it is also possible to pattern-form a gate insulating film together with the semiconductor layer correspondingly to the patterning of the gate electrode. Specifically, it is preferable to constitute the semiconductor layer and the gate insulating film so that they are formed in accordance with almost the same pattern as the case of the patterning of the gate electrode.
Moreover, a structure of a thin film transistor of the present invention is allowed to use not only the normal-stagger type (top-gate-type) but also the reverse-stagger type (bottom-gate type). In case of the reverse-stagger type (bottom-gate type), a gate electrode can be provided on a substrate and a semiconductor layer can be formed above the gate electrode through a gate insulating film as well as pattern-formed correspondingly to the patterning of the gate electrode. On the other hand, in case of the normal-stagger type (top-gate type), a semiconductor layer can be formed on a layer lower than a gate insulating film formed on the lower layer of a gate electrode. Application to the normal-stagger type (top-gate type) is particularly superior because the number of photomask steps can be easily reduced.
Moreover, by disposing a signal electrode at a position for preventing crosstalk running from an adjacent signal electrode to a pixel electrode through a semiconductor layer, it is possible to prevent a leak current from other signal line which should not flow into the pixel electrode. More specifically, it is preferable to dispose a signal electrode so as to isolate a gate electrode formed on an a-Si island from a gate line.
Furthermore, a thin film transistor of the present invention has a source electrode provided on a predetermined substrate, a drain electrode disposed by keeping a predetermined interval from the source electrode, a semiconductor layer disposed so as to contact the source electrode and drain electrode and connect the both electrodes, a gate insulating film for covering the semiconductor layer, and a gate electrode disposed so as to contact the gate insulating film. The gate electrode is provided with a protruded portion almost orthogonal to the source and drain electrodes so as to be patterned, the semiconductor layer and gate insulating film are pattern-formed in accordance with the patterning of the gate electrode, and the drain electrode is disposed at a position nearby the root of the protruded portion of the gate electrode for the source electrode.
In this case, when the semiconductor layer and gate insulating film are formed in the patterning step same as the case of the gate electrode, it is possible to prevent an extra current from running from an adjacent signal line (data line) into the source electrode through a gate line. Therefore, this is superior in that a display image can be prevented from deteriorating.
Moreover, the source electrode and the drain electrode are preferable in that it is possible to prevent inflow of crosstalk and it is possible to provide a thin film transistor free from fluctuation of stray capacitance even if a pattern shift occurs between a gate line and a signal line because the electrodes are arranged at a predetermined line width and in parallel with each other.
Furthermore, a liquid-crystal display panel of the present invention is a liquid-crystal display channel having a pixel electrode and a thin-film-transistor-channel structure for applying a voltage to the pixel electrode and provided with a gate line for forming a gate electrode in the thin-film-transistor-channel structure, a signal line to be connected to a signal electrode in the thin-film-transistor-channel structure, and a semiconductor layer to be patterned under a state along the gate line exceeding the thin-film-transistor-channel structure, in which the signal electrode is configured so as to prevent a current incoming from an adjacent signal line for applying a voltage to the pixel electrode and a pixel electrode adjacent to the former pixel electrode through the semiconductor layer.
In this case, because the semiconductor layer remains on the gate line and has a parasitic thin film transistor between the adjacent signal line and the thin-film-transistor-channel structure, a large operation/working effect is obtained in that crosstalk from an adjacent pixel electrode can be effectively prevented when etching a semiconductor layer by using gate-line resist or a gate-line plating pattern as a mask in a panel structure directly using a gate electrode as a gate wiring.
Moreover, a liquid-crystal display panel of the present invention is applied to not only a top-gate-type thin-film-transistor structure but also a bottom-gate-type thin-film-transistor structure. In case of the bottom-gate type, this gate electrode is formed on a substrate and the semiconductor layer is formed on a layer upper than a gate insulating film formed on the upper layer of the gate electrode. In case of the top-gate type, the semiconductor layer of it is formed on a layer lower than a gate insulating film formed on the lower layer of a gate electrode.
Furthermore, a thin-film-transistor manufacturing method of the present invention comprises the opaque film step of forming an opaque film having a predetermined shape on a substrate; the insulating film step of forming an insulating film on the substrate so as to cover the opaque film; the source-and drain-electrode forming step of forming a source electrode and a drain electrode made of metallic films having a predetermined line width and length and separated from each other by a predetermined interval; the semiconductor-and-insulating-film-layer forming step of forming a semiconductor layer and a gate insulating film layer in order on the insulating film above the source and drain electrodes, the gate-electrode forming step of forming a metallic film for a gate electrode on the gate insulating film layer; and the pattern forming step of patterning the semiconductor layer, gate insulating film layer, and metallic film for a gate electrode and thereby, forming a protruded TFT portion having a thin-film-transistor-channel structure and forming a semiconductor layer and a gate insulating film layer at a position of a gate electrode exceeding the protruded TFT portion; in which the source-and-drain-electrode forming step forms at least either of a source electrode and a drain electrode serving as a signal electrode so as to cross the protruded TFT portion formed in the pattern forming step.
Furthermore, in the thin-film-transistor manufacturing method, the pattern forming step pattern-forms a semiconductor layer, a gate insulating layer, and a metallic film for a gate electrode in the same patterning step. In other words, a pattern forming step of the present invention pattern-forms a semiconductor layer, a gate insulating film layer, and a metallic film for a gate electrode in almost the same shape. This feature is superior in that the number of necessary steps can be reduced in a thin-film-transistor manufacturing process capable of preventing an abnormal potential from being generated due to a leak current from other data lines.